Planar SiC Power Module Packaging and Interconnections Using Direct Ink Writing

被引:6
作者
Al-Haidari, Riadh [1 ]
Alhendi, Mohammed [1 ]
Richmond, Dylan [1 ]
Abbara, El Mehdi [1 ]
Obeidat, Abdullah [1 ]
Somarathna, Udara S. [1 ]
Schadt, Mark [1 ]
Poliks, Mark [1 ]
Gowda, Arun V. [2 ]
Erlbaum, Jeff [2 ]
Xiong, Han [2 ]
Hitchcock, Collin [2 ]
机构
[1] SUNY Binghamton, Binghamton, NY 13902 USA
[2] GE Global Res, Niskayuna, NY USA
来源
2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC | 2023年
关键词
Power Electronics; Silicon Carbide; Additive Manufacturing; Printed Electronics; Direct Ink Writing; Contact Resistance;
D O I
10.1109/ECTC51909.2023.00117
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Traditional device packaging becomes a limiting factor in realizing the full performance potential of SiC. Thus, improved and advanced packaging technologies are required to bridge the gap between SiC devices' potential and their applications. An additively printed electronics approach can enable advanced SiC power module packaging and interconnections. Printed electronics are being increasingly explored in the realm of electronics manufacturing, such as flexible hybrid electronics, and they have found their way into various aspects. However, printed electronics for high-power and high-performance power electronics is largely unexplored. Herein, we aim to develop a high planar power (>1.2kV), low profile, and low inductance SiC power module using conformal direct ink writing (DIW) interconnects and packaging. In addition, we aim to explore the feasibility and robustness of using printed electronics technologies for power packaging. The results of device-package simulations, dielectrics testing, conductor conductivity, and processing show the potential to meet high voltage requirements for SiC power modules. Functional vehicle testing shows that gate-source leakage, source-drain leakage, and threshold voltages are similar to conventionally packaged modules. In addition, functional test vehicles pass high voltage isolation and partial discharge tests. However, challenges in attaining high current capability remain due to high contact resistance between DIW interconnects and SiC chip and direct copper bonding (DCB) pads. Tailored surfaces and pressure sintering promise to attain lower contact resistance and on-resistance of the fabricated SiC modules.
引用
收藏
页码:668 / 675
页数:8
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