Design and Implementation of a Sense Amplifier for Low-Power Cardiac Pacemaker

被引:1
作者
Bikki, Pavankumar [1 ]
Dhiraj, Yenduri [2 ]
Kumar, R. V. S. Nivas [2 ]
机构
[1] BV Raju Inst Technol, Dept Elect & Commun, Narsapur, Telangana, India
[2] Natl Inst Technol Andhra Pradesh, Dept Elect & Commun, Tadepalligudem, Andhra Pradesh, India
关键词
Cardiac pacemaker; sense amplifier; instrumentation amplifier; band pass filter; comparator; QRS complex; DVCC;
D O I
10.1142/S0218126623501487
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents the implementation of a sense amplifier for a low-power cardiac pacemaker using the Differential Voltage Current Conveyor (DVCC). Two significant aspects of the pacemaker are sensing and pacing. The pulse generator, which is the heart of the pacemaker, consists of a sense amplifier, a logic unit and a timing control unit. The sense amplifier comprises an instrumentation amplifier, a bandpass filter and a comparator that are used to detect the QRS complex wave from the cardiac signal. Based on the output of a sense amplifier, the logic unit and the timing control unit decide whether to pace the heart or not, which achieves the requirement of the demand pacing. In this paper, a novel design of the sense amplifier using a DVCC is proposed, and the simulations are performed using 130-nm TSMC technology. Furthermore, the modes of the pacemaker VVI, DDD and rate-responsive algorithms have been implemented using the structural approach in VHDL by taking into consideration the timing cycles of a pacemaker. The design analysis shows that the proposed model of pacemaker is highly efficient and consumes significantly less energy.
引用
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页数:23
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