Improved approximate multiplier architecture for image processing and neural network

This paper proposes new approximate unsigned multiplier architecture which aims to reduce the power consumption and area with better accuracy. In our proposed design, the approximation is applied in partial product generation (PPG) and partial product reduction (PPR) stages. In PPG, we proposed two approximate sub-multipliers to reduce the number of partial product rows. For the 8-bit multiplier design, experimental results show an improvement of 38.78% and 50.53% in power and power-delay-product respectively, when the proposed design is compared against the exact design, and 26.11% and 33.17% respectively when compared to existing Ax8-1 design, without compromising on the accuracy. Finally, proposed designs are validated using image processing and neural network applications.