A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling

被引:0
|
作者
Wang, Qingxun [1 ]
Pan, Yuhan [1 ]
Chen, Kaiquan [1 ]
Lin, Yu [1 ]
Wang, Biao [2 ]
Qi, Liang [1 ]
机构
[1] Shanghai Jiao Tong Univ, Dept Micronano Elect, Shanghai, Peoples R China
[2] Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau, Peoples R China
来源
2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS | 2023年
基金
中国国家自然科学基金; 国家重点研发计划;
关键词
incremental analog-to-digital converter (IADC); linear-exponential; second-order noise coupling (NC); the effective data weighting averaging (DWA) and suppression of thermal noise;
D O I
10.1109/ISCAS46773.2023.10182049
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This paper presents a two-phase linear-exponential incremental analog-to-digital converter (IADC) with using second-order noise coupling (NC). In the first phase, it works as a first-order IADC. Then the second-order NC path is activated in the second phase to significantly expedite the accumulation speed. Moreover, during the second phase, the integrator is disabled to achieve a large maximum stable amplitude (MSA). Simulations demonstrated that the proposed architecture could achieve a higher signal-to-quantization-noise ratio (SQNR) while avoiding the noise penalty and keeping the high effectiveness of data weighting averaging (DWA) compared with the prior art with using first-order NC. Mathematical analysis and further simulation results are presented to confirm the theory of the proposed structure.
引用
收藏
页数:5
相关论文
共 50 条
  • [1] A Zoom Architecture Using Linear-Exponential Incremental ADC
    Wang, Qingxun
    Chenand, Kaiquan
    Qi, Liang
    2023 21ST IEEE INTERREGIONAL NEWCAS CONFERENCE, NEWCAS, 2023,
  • [2] A Two-step Linear-Exponential Incremental ADC with Slope Extended Counting
    Pan, Yuhan
    Wang, Qingxun
    Chen, Kaiquan
    Cai, Bin
    Qian, Jiuchao
    Lian, Yong
    Qi, Liang
    2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS, 2023,
  • [3] A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order
    Chen, Kaiquan
    Wang, Biao
    Liu, Yan
    Ye, Fan
    Sin, Sai-Weng
    Wang, Guoxing
    Lian, Yong
    Qi, Liang
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2023, 70 (08) : 2724 - 2728
  • [4] Modelling of two-phase flow with second-order accurate scheme
    Tiselj, I
    Petelin, S
    JOURNAL OF COMPUTATIONAL PHYSICS, 1997, 136 (02) : 503 - 521
  • [6] Second-order analysis by variograms for curvature measures of two-phase structures
    Arns, CH
    Mecke, J
    Mecke, K
    Stoyan, D
    EUROPEAN PHYSICAL JOURNAL B, 2005, 47 (03): : 397 - 409
  • [7] Second-order analysis by variograms for curvature measures of two-phase structures
    C. H. Arns
    J. Mecke
    K. Mecke
    D. Stoyan
    The European Physical Journal B - Condensed Matter and Complex Systems, 2005, 47 : 397 - 409
  • [8] A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer
    Oh, Taehwan
    Maghari, Nima
    Moon, Un-Ku
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (06) : 1465 - 1474
  • [9] A Second-Order Noise Shaping SAR ADC With Parallel Multiresidual Integrator
    Zhou, Yang
    Wang, Wenjie
    Zhu, Longbin
    Zhu, Zhengtao
    Su, Risheng
    Zheng, Jianan
    Xie, Siyuan
    Li, Jihong
    Meng, Fanyi
    Zhou, Zhijun
    Wang, Keping
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2024, 32 (11) : 2135 - 2138
  • [10] A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator
    Zhang, Qihui
    Ning, Ning
    Li, Jing
    Yu, Qi
    Wu, Kejun
    Zhang, Zhong
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 29 (01) : 227 - 231