Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation

被引：5

作者：

Roy, Saion K. ^{[1
]}

Ou, Han-Mo ^{[1
]}

Ahmed, Mostafa G. ^{[2
]}

Deaville, Peter ^{[3
]}

Zhang, Bonan ^{[3
]}

Verma, Naveen ^{[3
]}

Hanumolu, Pavan K. ^{[1
]}

Shanbhag, Naresh R. ^{[1
]}

机构：

[1] Univ Illinois, Urbana, IL 61801 USA

[2] Ain Shams Univ, Cairo, Egypt

[3] Princeton Univ, Princeton, NJ 08544 USA

来源：

IEEE 49TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE, ESSCIRC 2023 | 2023年

关键词：

eNVM; In-Memory Computing; Compute SNR; MRAM;

D O I：

10.1109/ESSCIRC59616.2023.10268688

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The accuracy of eNVM in-memory computing (IMC) designs is primarily limited by analog non-idealities. This paper presents an MRAM IMC macro in 22nm equipped with offset-compensating current sensing and a low-overhead statistical error compensation (SEC) block to boost its compute signal-to-noise ratio (SNR). The compute SNR reduces with an increase in inner-dimension of the MVM. An SEC-enabled SNR boost of 2.7-to-6 dB is obtained over different operating points. This boost can be traded-off to realize a 5x decrease in energy/1b-OP including an SEC energy overhead of 0.8%. Finally, we demonstrate an SEC-enabled neural network (NN) accuracy boost from 74.8% to 82.0% for CIFAR-10 over ResNet-20 without on-chip training.

引用

页码：25 / 28

页数：4

共 10 条

[1]

Deaville P., 2022, IEEE S VLSI CIRC

[2] A Maximally Row-Parallel MRAM In-Memory- Computing Macro Addressing Readout Circuit Sensitivity and Area [J].

Deaville, Peter ;

Zhang, Bonan ;

Chen, Lung-Yen ;

Verma, Naveen .

ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), 2021, :75-78

[3]

Hung J M, 2022, 2022 IEEE INT SOLID, P1, DOI 10.1109/ISSCC42614.2022.9731715

[4]

Khaddam-Aljameh R., 2021, 2021 Symposium on VLSI Circuits, V2021-June, DOI DOI 10.23919/VLSICIRCUITS52068.2021.9492362

[5]

Khwa W. -S., 2022, INT SOL STAT CIRC C, P1

[6] Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security [J].

Li, Wantong ;

Huang, Shanshi ;

Sun, Xiaoyu ;

Jiang, Hongwu ;

Yu, Shimeng .

2021 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2021,

[7] STT-MRAM Sensing: A Review [J].

Na, Taehui ;

Kang, Seung H. ;

Jung, Seong-Ook .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68 (01) :12-18

[8] Benchmarking In-Memory Computing Architectures [J].

Shanbhag, Naresh R. ;

Roy, Saion K. .

IEEE OPEN JOURNAL OF THE SOLID-STATE CIRCUITS SOCIETY, 2022, 2 :288-300

[9] 15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices [J].

Xue, Cheng-Xin ;

Huang, Tsung-Yuan ;

Liu, Je-Syu ;

Chang, Ting-Wei ;

Kao, Hui-Yao ;

Wang, Jing-Hong ;

Liu, Ta-Wei ;

Wei, Shih-Ying ;

Huang, Sheng-Po ;

Wei, Wei-Chen ;

Chen, Yi-Ren ;

Hsu, Tzu-Hsiang ;

Chen, Yen-Kai ;

Lo, Yun-Chen ;

Wen, Tai-Hsing ;

Lo, Chung-Chuan ;

Liu, Ren-Shun ;

Hsieh, Chih-Cheng ;

Tang, Kea-Tiong ;

Chang, Meng-Fan .

2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), 2020, :244-+

[10] A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection [J].

Yoon, Jong-Hyeok ;

Chang, Muya ;

Khwa, Win-San ;

Chih, Yu-Der ;

Chang, Meng-Fan ;

Raychowdhury, Arijit .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57 (01) :68-79

← 1 →