Impact of High-temperature and Interface Traps on Performance of a Junctionless Tunnel FET

Junctionless transistor (JLT) which does not have a PN junction in the source-channel-drain path, is reported to have a lower OFF-state current and therefore is more scalable to lower channel lengths compared to a conventional MOSFET, moreover a JLT also offers easy fabrication steps. Tunnel FET (TFET) provides a theoretically possible limit of subthreshold swing (SS) and has applicability for low-power electronics. Combining junctionless technology in a TFET (JL-TFET), the possible application of the device is looked into, for further low-power and high-temperature applications. This work analyses the performances of a JL-TFET for high-temperature applications and the same is compared with a conventional p-i-n siliconon-insulator tunnel field effect transistor (p-i-n SOI-TFET). Using calibrated technology computer-aided design (TCAD) simulations, analog circuit performance parameters like ON-state to OFF-state current ratio ( I-ON/I-OFF), subthreshold slope (SS), transconductance ( G(m)), gate-to-source capacitance ( C-GS), gate-to-drain capacitance ( C-GD), and cut-off frequency ( f T) etc. are analyzed for temperatures till 500 K. ON-state current of JL-TFET increases in the order of hundreds of mu A/mu m at high temperatures, whereas p- i-n SOI-TFET shows lesser temperature sensitivity. JL-FET is more applicable to low-power applications, whereas a p-i-n SOI-TFET has more suitability for high-speed applications. Dual material technology adoption helps in improving the ambipolar behavior of the device. Analysis of interface traps is carried out in this architecture where the concentration, energy positions, and energy width of the distribution of acceptor-like and donor-like traps at the interface of semiconductor and oxide are also evaluated.