Wafer map defect recognition based on multi-scale feature fusion and attention spatial pyramid pooling

被引:15
作者
Chen, Shouhong [2 ]
Huang, Zhentao [2 ]
Wang, Tao [2 ]
Hou, Xingna [1 ,2 ]
Ma, Jun [2 ]
机构
[1] Guilin Univ Elect Technol, Sch Architecture & Transportat Engn, Guilin, Peoples R China
[2] Guilin Univ Elect Technol, Sch Elect Engn & Automat, Guangxi Key Lab Automat Detecting Technol & Instr, Guilin, Peoples R China
基金
中国国家自然科学基金;
关键词
Wafer map classification; Pattern recognition; Attention spatial pyramid pooling; Semiconductor manufacturing; CONVOLUTIONAL NEURAL-NETWORK; PATTERN-RECOGNITION; IDENTIFICATION; CLASSIFICATION;
D O I
10.1007/s10845-023-02231-z
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Wafers are products in semiconductor manufacturing and serve as the foundation for producing semiconductor chips. During the wafer testing stage, functional and electrical parameters are examined to identify defects in chip design and fabrication. The wafer map is the result of the wafer testing process. Analyzing and classifying defective information on the wafer map aids in defect source identification and optimization of the wafer production process. Deep learning has been employed for defect detection on wafer maps because of its superior image processing capabilities. Nevertheless, as semiconductor chip design integration and wafer size increase, more complex types of wafer defects tend to emerge in the production process, and the size, shape, and distribution of wafer defects can affect the final classification outcome. Accordingly, this study proposes a deep learning model, called ESPP-Net (Attention Spatial Pyramid Pooling Network), that combines a deep convolutional neural network and attention space pyramid pooling to recognize and classify single and mixed-type defect wafer maps. We evaluated our model on both the mixed-type dataset Mixed38WM and the single-type dataset WM-811K and compared it with state-of-the-art deep learning models. Experimental results show that our proposed model outperformed the preexisting models and demonstrated superior classification performance.
引用
收藏
页码:271 / 284
页数:14
相关论文
共 35 条
[1]  
Batool U, 2020, 2020 16TH IEEE INTERNATIONAL COLLOQUIUM ON SIGNAL PROCESSING & ITS APPLICATIONS (CSPA 2020), P230, DOI [10.1109/cspa48992.2020.9068669, 10.1109/CSPA48992.2020.9068669]
[2]  
Biswas S., 2022, 2022 IEEE REG 10 S T, P1, DOI [10.1109/TENSYMP54529.2022.9864391, DOI 10.1109/TENSYMP54529.2022.9864391]
[3]   Wafer map defect pattern detection method based on improved attention mechanism [J].
Chen, Shouhong ;
Liu, Meiqi ;
Hou, Xingna ;
Zhu, Ziren ;
Huang, Zhentao ;
Wang, Tao .
EXPERT SYSTEMS WITH APPLICATIONS, 2023, 230
[4]   Wafer map failure pattern recognition based on deep convolutional neural network [J].
Chen, Shouhong ;
Zhang, Yuxuan ;
Hou, Xingna ;
Shang, Yuling ;
Yang, Ping .
EXPERT SYSTEMS WITH APPLICATIONS, 2022, 209
[5]   AI classification of wafer map defect patterns by using dual-channel convolutional neural network [J].
Chen, Shouhong ;
Zhang, Yuxuan ;
Yi, Mulan ;
Shang, Yuling ;
Yang, Ping .
ENGINEERING FAILURE ANALYSIS, 2021, 130
[6]   A self-adaptive DBSCAN-based method for wafer bin map defect pattern classification [J].
Chen, Shouhong ;
Yi, Mulan ;
Zhang, Yuxuan ;
Hou, Xingna ;
Shang, Yuling ;
Yang, Ping .
MICROELECTRONICS RELIABILITY, 2021, 123
[7]   Convolutional Neural Network for Wafer Surface Defect Classification and the Detection of Unknown Defect Class [J].
Cheon, Sejune ;
Lee, Hankang ;
Kim, Chang Ouk ;
Lee, Seok Hyung .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2019, 32 (02) :163-170
[8]   Applying Data Augmentation and Mask R-CNN-Based Instance Segmentation Method for Mixed-Type Wafer Maps Defect Patterns Classification [J].
Chiu, Ming-Chuan ;
Chen, Tao-Ming .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2021, 34 (04) :455-463
[9]   Fault Diagnosis of Wafer Acceptance Test and Chip Probing Between Front-End-of-Line and Back-End-of-Line Processes [J].
Fan, Shu-Kai S. ;
Cheng, Chun-Wei ;
Tsai, Du-Ming .
IEEE TRANSACTIONS ON AUTOMATION SCIENCE AND ENGINEERING, 2022, 19 (04) :3068-3082
[10]   Monitoring wafer map data from integrated circuit fabrication processes for spatially clustered defects [J].
Hansen, MH ;
Nair, VN ;
Friedman, DJ .
TECHNOMETRICS, 1997, 39 (03) :241-253