Advances and Trends on On-Chip Compute-in-Memory Macros and Accelerators

被引：0
|
作者：
Seo, Jae-sun [1 ,2 ]
机构：
[1] Arizona State Univ, Sch ECEE, Tempe, AZ 85281 USA
[2] Meta Real Labs, Tempe, AZ 85287 USA
来源：
2023 60TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC | 2023年
关键词：
Compute-in-memory; AI; accelerator; ASIC;
D O I：
10.1109/DAC56929.2023.10248014
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Conventional AI accelerators have been bottle-necked by high volumes of data movement and accesses required between memory and compute units. A transformative approach that has emerged to address this in compute-in-memory (CIM) architectures, which perform computation in-place inside the volatile or non-volatile memory in an analog or digital manner, greatly reducing the data transfers and memory accesses. This paper presents recent advances and trends on CIM macros and CIM-based accelerator designs.
引用
收藏
页数：2
相关论文
共 50 条
  • [21] CoMeFa: Compute-in-Memory Blocks for FPGAs
    Arora, Aman
    Anand, Tanmay
    Borda, Aatman
    Sehgal, Rishabh
    Hanindhito, Bagus
    Kulkarni, Jaydeep
    John, Lizy K.
    2022 IEEE 30TH INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2022), 2022, : 45 - 53
  • [22] A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References
    Li, Wantong
    Sun, Xiaoyu
    Jiang, Hongwu
    Huang, Shanshi
    Yu, Shimeng
    ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), 2021, : 79 - 82
  • [23] A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References
    Li, Wantong
    Sun, Xiaoyu
    Jiang, Hongwu
    Huang, Shanshi
    Yu, Shimeng
    IEEE 51ST EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2021), 2021, : 79 - 82
  • [24] Harnessing Emerging Technology for Compute-In-Memory Support
    Jao, Nicholas
    Ramanathan, Akshay Krishna
    Srinivasa, Srivatsa
    George, Sumitha
    Sampson, John
    Narayanan, Vijaykrishnan
    2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2018, : 447 - 452
  • [25] Photonic Tensor Core with Photonic Compute-in-Memory
    Ma, Xiaoxuan
    Meng, Jiawei
    Peserico, Nicola
    Miscuglio, Mario
    Zhang, Yifei
    Hu, Juejun
    Sorger, Volker J.
    2022 OPTICAL FIBER COMMUNICATIONS CONFERENCE AND EXHIBITION (OFC), 2022,
  • [26] From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits
    Zhaoyang ZHANG
    Jinwu CHEN
    Xi CHEN
    An GUO
    Bo WANG
    Tianzhu XIONG
    Yuyao KONG
    Xingyu PU
    Shengnan HE
    Xin SI
    Jun YANG
    Science China(Information Sciences), 2023, 66 (10) : 42 - 60
  • [27] Approximate Adder Tree Design with Sparsity-Aware Encoding and In-Memory Swapping for SRAM-based Digital Compute-In-Memory Macros
    Lin, Ming-Guang
    Wang, Jiing-Ping
    Chang, Cheng-Yang
    Wu, An-Yeu
    2024 IEEE 6TH INTERNATIONAL CONFERENCE ON AI CIRCUITS AND SYSTEMS, AICAS 2024, 2024, : 362 - 366
  • [28] Compute-In-Memory Technologies for Deep Learning Acceleration
    Meng, Fan-husan
    Lu, Wei D.
    IEEE NANOTECHNOLOGY MAGAZINE, 2024, 18 (01) : 44 - 52
  • [29] Compute-in-Memory for Al: From Inference to Training
    Yu, Shimeng
    2020 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2020,
  • [30] From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits
    Zhang, Zhaoyang
    Chen, Jinwu
    Chen, Xi
    Guo, An
    Wang, Bo
    Xiong, Tianzhu
    Kong, Yuyao
    Pu, Xingyu
    He, Shengnan
    Si, Xin
    Yang, Jun
    SCIENCE CHINA-INFORMATION SCIENCES, 2023, 66 (10)
12345