Advances and Trends on On-Chip Compute-in-Memory Macros and Accelerators

被引：0
|
作者：
Seo, Jae-sun [1 ,2 ]
机构：
[1] Arizona State Univ, Sch ECEE, Tempe, AZ 85281 USA
[2] Meta Real Labs, Tempe, AZ 85287 USA
来源：
2023 60TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC | 2023年
关键词：
Compute-in-memory; AI; accelerator; ASIC;
D O I：
10.1109/DAC56929.2023.10248014
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Conventional AI accelerators have been bottle-necked by high volumes of data movement and accesses required between memory and compute units. A transformative approach that has emerged to address this in compute-in-memory (CIM) architectures, which perform computation in-place inside the volatile or non-volatile memory in an analog or digital manner, greatly reducing the data transfers and memory accesses. This paper presents recent advances and trends on CIM macros and CIM-based accelerator designs.
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页数：2
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