Scalable Photonic Digital-to-Analog Converters

This work introduces a novel architecture for implementing a parallel coherent photonic digital-to-analog converter (PDAC), designed to transform parallel digital electrical signals into corresponding analog optical output, convertible to analog electrical signals using photodiodes. The proposed architecture incorporates microring resonator-based modulators (MRMs), phase shifters, and symmetric multimode interference couplers. Efficient modulation is achieved by MRMs utilizing carrier depletion-induced refractive index changes, while metal heaters facilitate tuning of the ring resonator resonance wavelength. The proposed architecture is scalable to higher bit resolutions and exhibits a dynamic range limited by MRM's sensitivity to applied bias and noise levels. Experimental results of the fabricated chip in the silicon-on-insulator (SOI) platform showcase the successful realization of a 4 GSample/sec conversion rate in a 2-bit resolution operation, along with a stationary conversion of four parallel DC digital signals into 16 analog intensity levels in a 4-bit PDAC configuration. The study encompasses a proof-of-concept experimental demonstration of 8 Gbps data conversion, along with a 50 Gbps data conversion rate using the optimized design in the simulation, affirming the accuracy and quality of the PDAC architecture. These findings contribute to the advancement of PDAC technology, providing insights into performance characteristics, limitations, and potential applications.