A low-power low-dropout regulator with improved transient response and power supply rejection

A high-precision fast-settling low-dropout (LDO) regulator has been presented in this paper. A novel frequency compensation scheme has been proposed to acquire wider bandwidth while sufficient stability is guaranteed for all loading conditions without using external compensation capacitors. Moreover, novel auxiliary circuits have been proposed to improve the slew rate and minimize the settling time. The new LDO has been designed in a standard 0.18-mu m CMOS process. Postlayout simulation results show that the LDO achieves 2.7- and 2.48-MHz unity-gain frequency for 100 and 0 mA of load current, respectively, while the minimum phase margin is 64 degrees. The results also demonstrate that the worst-case settling time is almost equal to 1.95 mu s. It is shown that by using the new slew rate enhancement technique, the settling time has been reduced from 18 to 1.9 mu s. The LDO consumes a quiescent current of 21.5 mu A, and the power supply rejection is -46 dB at 10-kHz offset, which makes the LDO capable of adequately suppressing input supply ripples. The large loop gain of the proposed circuit improves the accuracy of the LDO, and the load and line regulations are 0.1 mV/mA and 0.1 mV/V, respectively. A high-precision fast-settling low-dropout (LDO) regulator has been presented. A novel frequency compensation scheme has been proposed to acquire wider bandwidth while sufficient stability is guaranteed without using external compensation capacitors. Moreover, new auxiliary circuits have been proposed to improve the slew rate and minimize the settling time.image