CMOS phase-locked loops in ISSCC 2023

被引：1
|
作者：
Zhang, Zhao [1 ,2 ]
机构：
[1] Chinese Acad Sci, Inst Semicond, State Key Lab Superlatt & Microstruct, Beijing 100083, Peoples R China
[2] Univ Chinese Acad Sci, Ctr Mat Sci & Optoelect Engn, Beijing 100049, Peoples R China
来源：
JOURNAL OF SEMICONDUCTORS | 2023年 / 44卷 / 05期
基金：
中国国家自然科学基金;
关键词：
Compendex;
D O I：
10.1088/1674-4926/44/5/050205
中图分类号：
O469 [凝聚态物理学];
学科分类号：
070205 ;
摘要：
As discussed previously, PLLs reported in ISSCC 2023 shows several design trends, including design digit-al-intensive calibration, cascading several stage PLLs with different architectures, performance improvement with reference frequency multiplication, and high-performance design with lower supply voltage using multi-path architectures. Hence, in summary, the PLL future performance improvements rely more and more on the architecture and circuit in-novation rather than new process. © 2023 Chinese Institute of Electronics.
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收藏
页数：2
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