LOLA SDR: Low Power Low Latency Software Defined Radio for Broadcast Audio Applications

被引:2
作者
Etrillard, Olivier [1 ]
Gerzaguet, Robin [2 ]
Feichter, Laurent [1 ]
Mabon, Malo [2 ]
Courtay, Antoine [2 ]
Berder, Olivier [2 ]
机构
[1] Feichter Elect, F-22300 Lannion, France
[2] Univ Rennes, CNRS, IRISA, F-22300 Lannion, France
关键词
Computer architecture; Field programmable gate arrays; Low latency communication; Coprocessors; Software; Costs; Receivers; Software defined radio; microcontroller; audio processing; low power; low latency; PLATFORM;
D O I
10.1109/TCSII.2022.3175569
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This brief proposes a new low power, low latency and low cost reconfigurable architecture for software defined radio. Due to their flexibility and reconfigurability, software defined radios are now massively used as wideband transceivers, channel sounders or network gateways. However, they often struggle to meet the desired requirements in terms of energy consumption and throughput. In this brief, we present a new architecture capable of tackling these challenges, by combining an off-the-shelf generic radio component with a low power micro controller associated to a Fourier transform coprocessor. To prove the benefit of our approach, after describing the key assets of the architecture, we derive a complete physical layer dedicated to audio broadcast applications. This chain is capable of streaming High Definition audio stream in real time with low power (437 mW) and very low latency (854 mu s). We show that our processing chain can be flawlessly run on our architecture paving the way for larger adoption of a new generation of low power low latency software defined radio architectures.
引用
收藏
页码:481 / 485
页数:5
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