Dimensional Effect on Analog/RF Performance of Dual Material Gate Junctionless FinFET at 7 nm Technology Node

Fully Depleted Silicon On Insulator (FDSOI) structures are present-era technology as it has enhanced control over Short Channel Effects in the sub-nanometre regime. This paper studies the analog and radio frequency performance of junctionless FinFET with dual material gate (DMG JLFinFET) based on FDSOI for low power applications. We extracted analog and radio frequency parameters with the variation of fin height (F-H = 10 nm to 30 nm) and fin width (F-W = 46 nm). The parameters like transconductance (g(m)), transconductance generation factor, cut-off frequency (f(T)), intrinsic delay (tau), gate capacitance (C-gg), gate to source capacitance (C-gs), gate to drain capacitance (C-gd), and transconductance frequency product, gain bandwidth product are calculated. At F-H = 6 nm all the parameters are increased except time delay which was small decrement. Similarly for F-W also all the parameters are improved with increment of fin width except time delay. In contempt C-gd and C-gg are less impact on dimensional variation. From this study it reveals that, in FinFET design, designers have to consider dimensional variations in Anlog/RF parameters and FinFET is suitable candidate for nano scale low power Anlog/RF applications. In this work all these simulations are carried out by Cogenda Visual TCAD.