An Attachable Fractional Divider Transforming an Integer-N PLL Into a Fractional-N PLL Achieving Only 0.35-psrms-Integrated-Jitter Degradation With SSC Capability

被引：2

作者：

Motozawa, Atsushi ^{[1
]}

Hiraku, Yasuyuki ^{[1
]}

Hirai, Yoshitaka ^{[1
]}

Hiyama, Naoaki ^{[1
]}

Imanaka, Yusuke ^{[1
]}

Morishita, Fukashi ^{[1
]}

机构：

[1] Renesas Elect Corp, IoT & Infrastruct Business Unit, Tokyo 1878588, Japan

来源：

IEEE SOLID-STATE CIRCUITS LETTERS | 2023年 / 6卷

关键词：

Phase locked loops; Voltage-controlled oscillators; Clocks; Generators; Global navigation satellite system; Pulse generation; Industries; Electromagnetic interference (EMI); fractional divider (FDIV); fractional spur; fractional-N PLL (Frac-N PLL); integer-N PLL (Int-N PLL); phase interpolator (PI); spread-spectrum clocking (SSC);

D O I：

10.1109/LSSC.2023.3254521

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Phase-locked loops (PLLs) are utilized in SoCs for the automotive industry. In the industry, the system handles with satellite signals which are weak radio waves coming from space. Therefore, the output frequency of PLLs is carefully designed to avoid electromagnetic interference (EMI). Recently, the global navigation satellite system (GNSS) is becoming more common and available frequency bands for clocks are getting narrow. That leads, in many products, replacement integer-N PLLs (Int-N PLLs) with fractional-N PLLs (Frac-N PLLs) are needed to obtain smaller output frequency steps than reference frequency. The attachable fractional divider proposed in this letter transforms an Int-N PLL into a Frac-N PLL with only 0.35 psrms of integrated RMS jitter degradation.

引用

页码：69 / 72

页数：4

共 13 条

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