PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era

The ever-increasing rate of static power consumption in nanoscale technologies, and consequently, the breakdown of Dennard scaling acts as a power wall for further device scaling. With intensified power density, designers are forced to selectively power off portions of chip area, known as dark silicon. With significant power consumption of routing resources in the field-programmable gate array (FPGA) and their low utilization rate, power gating of unused routing resources can be used to reduce the overall device power consumption. While power gating has taken great attention, previous studies neglect major factors that affect the effectiveness of power gating, for example, routing architecture, topology, and technology. In this article, we propose a power-efficient routing architecture (PERA) for SRAM-based FPGAs, which is designed pursuant to the utilization pattern of routing resources with different topologies. PERA is applicable to different granularity from a multiplexer to a switch-matrix (SM) level. We examine the efficiency of the proposed architecture with different topologies, structures, and parameters of routing resources. We further propose a routing algorithm to reduce the scattered use of resources and hence to take advantage of opportunities of power gating in routing resources. Our experiments using a versatile place and route (VPR) toolset on the FPGA architecture similar to commercial chips over an extensive set of circuits from Microelectronics Center of North Carolina (MCNC), International Workshop on Logic Synthesis (IWLS), Verilog to routing (VTR), and Titan benchmarks indicate that PERA reduces the static power consumption by 43.3%. This improvement is obtained at the expense of 7.4% area overhead. PERA along with the optimized routing algorithm offers a total routing leakage power reduction of up to 64.9% when compared to nonpower-gating architectures and 6.9% when compared with the conventional routing algorithm across all benchmark circuits and architectures with various wire segment lengths. This is while the optimized routing algorithm degrades performance by only less than 3%.