A Framework for Design, Verification, and Management of SoC Access Control Systems

被引:5
作者
Restuccia, Francesco [1 ]
Meza, Andres [2 ]
Kastner, Ryan
Oberg, Jason
机构
[1] Univ Calif San Diego, La Jolla, CA 92093 USA
[2] Univ Calif San Diego, Comparat Cognit Lab, La Jolla, CA 95134 USA
关键词
Access control; System-on-chip; Hardware; Microprogramming; IP networks; Engines; Safety; Access control systems; system-on-chip architectures; security verification; safety-critical systems; security-critical systems; ARCHITECTURE; SECURITY;
D O I
10.1109/TC.2022.3209923
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
System-on-chip (SoC) architectures are a heterogeneous mix of microprocessors, custom accelerators, memories, interfaces, peripherals, and other resources. These resources communicate using complex on-chip interconnect networks that attempt to quickly and efficiently arbitrate memory transactions whose behaviors can vary drastically depending on the current mode of operation and system operating state. Security- and safety-critical applications require access control policies that define how these resources interact to ensure that malicious and unsafe behaviors do not occur. Aker is a design and verification framework for on-chip access control. The core of Aker is the access control wrapper (ACW)-a high-performance yet efficient hardware module that dynamically arbitrates on-chip communications. Aker distributes ACWs across the SoC and programs them to perform local access control. Aker provides a firmware generation tool and a property-driven security verification methodology to ensure that the ACWs are properly integrated and configured. Aker security verification confirms that the ACW behaves properly at IP level. It verifies the hardware root of trust firmware configures the ACW correctly. And it evaluates system-level security threats due to interactions between shared resources. Aker is experimentally validated on a Xilinx UltraScale+ programmable SoC. Additionally, an Aker access control system is integrated into the OpenPULP multicore archtiecture that uses OpenTitan hardware root-of-trust for firmware configuration.
引用
收藏
页码:386 / 400
页数:15
相关论文
共 43 条
[21]   Toward Hardware Security Property Generation at Scale [J].
Deutschbein, Calvin ;
Meza, Andres ;
Restuccia, Francesco ;
Gregoire, Matthew ;
Kastner, Ryan ;
Sturton, Cynthia .
IEEE SECURITY & PRIVACY, 2022, 20 (03) :43-51
[22]   Secure memory accesses on Networks-on-Chip [J].
Fiorin, Leandro ;
Palermo, Gianluca ;
Lukovic, Slobodan ;
Catalano, Valerio ;
Silvano, Cristina .
IEEE TRANSACTIONS ON COMPUTERS, 2008, 57 (09) :1216-1229
[23]   Security in MPSoCs: A NoC Firewall and an Evaluation Framework [J].
Grammatikakis, Miltos D. ;
Papadimitriou, Kyprianos ;
Petrakis, Polydoros ;
Papagrigoriou, Antonis ;
Kornaros, George ;
Christoforakis, Ioannis ;
Tomoutzoglou, Othon ;
Tsamis, George ;
Coppola, Marcello .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (08) :1344-1357
[24]   Hardware Information Flow Tracking [J].
Hu, Wei ;
Ardeshiricham, Armaiti ;
Kastner, Ryan .
ACM COMPUTING SURVEYS, 2021, 54 (04)
[25]   Property Specific Information Flow Analysis for Hardware Security Verification [J].
Hu, Wei ;
Ardeshiricham, Armaiti ;
Gobulukoglu, Mustafa S. ;
Wang, Xinmu ;
Kastner, Ryan .
2018 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) DIGEST OF TECHNICAL PAPERS, 2018,
[26]   Towards Property Driven Hardware Security [J].
Hu, Wei ;
Althoff, Alric ;
Ardeshiricham, Armaiti ;
Kastner, Ryan .
2016 17TH INTERNATIONAL WORKSHOP ON MICROPROCESSOR AND SOC TEST AND VERIFICATION (MTV), 2016, :51-56
[27]   Enforcing memory policy specifications in reconfigurable hardware [J].
Huffmire, Ted ;
Sherwood, Timothy ;
Kastner, Ryan ;
Levin, Timothy .
COMPUTERS & SECURITY, 2008, 27 (5-6) :197-215
[28]  
Huffmire T, 2006, LECT NOTES COMPUT SC, V4189, P461
[29]  
Jacob N, 2017, DES AUT TEST EUROPE, P1122, DOI 10.23919/DATE.2017.7927157
[30]  
Nath APD, 2018, ASIA S PACIF DES AUT, P733, DOI 10.1109/ASPDAC.2018.8297409