A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

被引:6
作者
Butola, Rajat [1 ]
Li, Yiming [1 ]
Kola, Sekhar Reddy [1 ,2 ]
机构
[1] Natl Yang Ming Chiao Tung Univ, Elect Engn & Comp Sci Int Grad Program, Parallel & Sci Comp Lab, Hsinchu, Taiwan
[2] Natl Yang Ming Chiao Tung Univ, Inst Biomed Engn, Inst Pioneer Semicond Innovat, Dept Elect & Elect Engn,Inst Commun Engn, Hsinchu 300093, Taiwan
来源
IEEE OPEN JOURNAL OF NANOTECHNOLOGY | 2023年 / 4卷
关键词
Integrated circuit modeling; Adaptation models; Semiconductor device modeling; Data models; Nanoscale devices; Computational modeling; Predictive models; Adaptive neural network; circuit simulation; dynamic weights; gate-all-around; MOSFET; nanodevice; nanosheet; process variability; ARTIFICIAL NEURAL-NETWORK; SOURCE/DRAIN; FINFET;
D O I
10.1109/OJNANO.2023.3328425
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domain. One major advantage of ML-based compact modeling is its ability to capture complex relationships and patterns in large datasets. Therefore, in this paper a novel design scheme based on dynamically adaptive neural network (DANN) is proposed to develop fast and accurate compact model (CM). This framework constitutes a powerful yet computationally efficient methodology and exhibits emergent dynamic behaviors. This paper demonstrates that the compact model based on ML can be designed to replicate the performance of conventional compact model for nanodevices. For this work, gate-all-around (GAA) nanosheet (NS) device characteristics are comprehensively analyzed for process variability sources using the proposed model. The device geometry parameters such as channel length, nanosheet width and nanosheet thickness are fed as input features to the DANN model. The adaptive neural network learns dynamically by updating weights of the model in accordance with the input features and achieves accurate neural weight convergence. The proposed model predicted the electrical characteristics of NS devices with less than 1% error rate. The model is also implemented and validated for the simulations of digital circuit designs such as inverter, and logic gates.
引用
收藏
页码:181 / 194
页数:14
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