Adaptive Hybrid Framework for Multiscale Void Inspection of Chip Resistor Solder Joints

During reflow soldering, voids inevitably emerge inside the solder joints of chip resistors, which will influence the reliability of the electronic device. In this article, an adaptive hybrid framework is proposed for multiscale void inspection of chip resistor solder joints. First, an adaptive partition scheme is proposed to adaptively divide the image of the chip resistor solder joint into two regions, which correspond to the solder beneath the chip resistor body (Region 1) and the solder fillet (Region 2). Then, the voids in the two regions are separately inspected by two proposed adaptive inspection methods. One is that the multiscale convolution with adaptive circular kernels (MC-ACKs), guided filtering, and thresholding segmentation is proposed to inspect the voids in Region 1. The other is that an improved active contour model (ACM) is proposed to inspect the voids in Region 2, which incorporates the gray adaptive strategy and shape prior (SP) of the void. Finally, the shape factor and average gray strategy are utilized for void fine inspection of the chip resistor solder joint. Experimental results indicate that the proposed framework is superior to some existing methods, with an inspection performance of 0.9069 average Dice coefficient, 0.9907 F1 score, and 98.51% accuracy at a reasonable inspection speed.