A novel time delay-based phase-locked loop with improved anti-harmonic interference performance for grid synchronization

被引:0
作者
An, Dingguo [1 ]
Yuan, Lifen [1 ,3 ]
Cheng, Zhen [1 ,3 ]
He, Yigang [2 ]
Yin, Baiqiang [1 ]
Li, Bing [1 ]
机构
[1] Hefei Univ Technol, Sch Elect Engn & Automat, Hefei, Peoples R China
[2] Wuhan Univ, Sch Elect Engn, Wuhan, Peoples R China
[3] Hefei Univ Technol, Sch Elect Engn & Automat, Hefei 230009, Peoples R China
基金
中国国家自然科学基金;
关键词
grid synchronization; phase-locked loop; quadrature signal generation; single phase;
D O I
10.1002/cta.3733
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The time delay unit-based PLLs (TD-PLLs) are widely used in grid synchronization in single-phase power systems. However, the TD-PLL is vulnerable to frequency variations and harmonic disturbances, leading to grid synchronization failures. Analysis shows that the performance degradation is due to the inability to obtain the variation of the input signal frequency. This paper proposes a new time delay-based phase-locked loop called immune to double frequency component TD-PLL (IDFC-TD-PLL) based on a feedback structure to accurately capture the variation of input signal frequency, which can improve the dynamic performance and the performance against harmonic interference. Simulations and experiments have evaluated the performance of the proposed phase-locked loop, demonstrating its superior accuracy and dynamic performance compared to the phase-locked loops referred in the paper.
引用
收藏
页码:5634 / 5649
页数:16
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