Execution of stored programs by a rapid single-flux-quantum random-access-memory-embedded bit-serial microprocessor using 50-GHz clock frequency

被引:8
作者
Tanaka, Masamitsu [1 ]
Sato, Ryo [1 ]
Fujimaki, Akira [1 ]
Takagi, Kazuyoshi [2 ,3 ]
Takagi, Naofumi [2 ]
机构
[1] Nagoya Univ, Dept Elect, Furo Cho,Chikusa Ku, Nagoya 4648603, Japan
[2] Kyoto Univ, Dept Informat, Yoshida Honmachi,Sakyo Ku, Kyoto 6068501, Japan
[3] Mie Univ, Dept Informat Engn, 1577 Kurimamachiya Cho, Tsu 5148507, Japan
关键词
DESIGN; IMPLEMENTATION; CIRCUITS; CHIP;
D O I
10.1063/5.0148273
中图分类号
O59 [应用物理学];
学科分类号
摘要
We have demonstrated the execution of several programs stored in an instruction memory by a rapid single-flux-quantum bit-serial 8-bit microprocessor named CORE e2h. We employed a minimal instruction set architecture composed of 13 instructions based on the reduced instruction set computer. We integrated a 128-bit instruction memory and a 128-bit data memory with an arithmetic logic unit, two registers, a program counter, an instruction register, and a controller unit on a single chip. The bit-serial operation was performed by an on-chip clock generator, while the system clocks are provided from room-temperature electronics. The CORE e2h was made up of 11 000 Nb/AlOx/Nb Josephson junctions and fabricated with the Advanced Industrial Science and Technology 10-kA/cm(2), 9-Nb-layer process. We obtained the correct results for all the executed programs, including the integer division, the two kinds of summation algorithms, the Euclidean algorithm, and finding the greatest divisor. These test programs contained a single or nested double loop, and the maximum number of executed instructions was 205. We confirmed the stable operation with the DC bias margins of around 10% at 50-GHz for different test programs. The measured electric power consumption was 2.5 mW at 4.2 K, and the estimated computing power was 500 x 10(6) instructions/s.
引用
收藏
页数:5
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