RFAM: RESET-Failure-Aware-Model for HfO2-based Memristor to Enhance the Reliability of Neuromorphic Design

Memristors are a suitable candidate to design synapse circuits and neuromorphic systems. Due to device and voltage variability, operating a memristive device with reliability is a big challenge. To enhance the reliability of memristive synapse, RESET failure needs to be considered. In this work, we are focused on RESET failure modeling with RESET voltage variation. Here, the RESET failure is defined as hard failure of the memristive synapse due to a high RESET voltage being applied. The proposed Verilog-A model is derived based on experimental data collected from 1T1R devices, which are fabricated on 65 nm CMOS process. To enhance the reliability of system-level simulation, this device model will provide better guidelines to the designer. In addition, power consumption for a successful RESET operation is 7.065 mu W at 1.5 V, which can RESET the memristor resistance from 5 k ohm to 200 k ohm.