MULTI-CHIP COUPLING THERMAL RESISTANCE TOPOLOGICAL NETWORK MODEL AND CHIP JUNCTION TEMPERATURE PREDICTION OF SYSTEM IN PACKAGE

Multiple heat sources and complex thermal coupling exist in a highly integrated system in package (SiP), making it difficult to predict the junction temperature inside a multi-chip SiP. Here, we develop a mathematical model to calculate the internal thermal resistance and predict the junction temperature of a multi-chip SiP. Based on the model, the heat flow path of the internal chip heat dissipation is clarified and a thermal resistance topology network is established. The concept of coupling and spreading thermal resistance is also proposed for the multi-chip thermal coupling effect and heat diffusion effect. Computational fluid dynamics (CFD) simulation is conducted for comparison with model calculation at ambient temperature of 25 & DEG;C and under natural convection heat dissipation conditions. It can be found that the results obtained by model calculation are consistent with the simulation results, the average error of the junction temperature of each chip is only 5.69 & DEG;C and the error of the highest chip junction temperature is 9.71 & DEG;C, which means the accuracy of the calculated results is acceptable and reliable. Based on the above model, the chip junction temperature under different external conditions is calculated and predicted to study the influence of factors such as ambient temperature and cooling air speed on the chip junction temperature. This work is expected to provide theoretical support for the thermal design and thermal management of chips.