Using Logging-on-Write to Improve Non-Volatile Memory Checkpoints via Processing-in-Memory

被引:0
作者
Kruger, Kleber [1 ]
Pannain, Ricardo [1 ]
Azevedo, Rodolfo [1 ]
机构
[1] Univ Estadual Campinas, Inst Comp, Campinas, Brazil
来源
2023 IEEE 35TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING, SBAC-PAD | 2023年
基金
巴西圣保罗研究基金会;
关键词
processing-in-memory; in-memory computing; non-volatile memory; checkpointing; crash consistency;
D O I
10.1109/SBAC-PAD59825.2023.00016
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
NVM architectures must keep consistent data in case of failures, a property called crash consistency. A common way to do so is by checkpoint mechanisms. However, most of the strategies developed have performance and usability problems. Among main limitations are non-software-transparent strategies, the addition of logging operations in the critical execution path, and increased writes to NVM, resulting in significant bandwidth usage between processor and memory. DONUTS solves these problems by a hardware mechanism that provides crash consistency via checkpoints integrated into cache replacement policy using Processing-in-Memory to perform logging operations. Its approach reduces writes from the processor's memory controller and the NVM external bandwidth usage but generates unnecessary log entries. This paper expands DONUTS to a multi-core scenario evaluating two processing-in-memory strategies. The first logs during read operations, and the second uses a new lazy strategy to log data exclusively on write operations when these operations are effectively needed. Finally, we compare runtime performance, log rate, energy consumption, and memory space. Results show that our new logging-on-write strategy maintained the DONUTS runtime performance but reduced energy consumption in multi-core applications by around 33% due to an average reduction of 42% in log operations. Also, the new strategy generates a checkpoint size 5x smaller than the previous system, maximizing the use of NVM. Compared to other systems, DONUTS presented an average overhead of 1% to 3% against up to 7% of previous software-transparent better-performing projects.
引用
收藏
页码:68 / 77
页数:10
相关论文
共 46 条
[1]   Compute Caches [J].
Aga, Shaizeen ;
Jeloka, Supreet ;
Subramaniyan, Arun ;
Narayanasamy, Satish ;
Blaauw, David ;
Das, Reetuparna .
2017 23RD IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2017, :481-492
[2]  
Angizi S., 2018, 2018 55 ACM ESDA IEE, P1
[3]   AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM [J].
Angizi, Shaahin ;
Sun, Jiao ;
Zhang, Wei ;
Fan, Deliang .
PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2019,
[4]   CMP-PIM: An Energy-Efficient Comparator-based Processing-In-Memory Neural Network Accelerator [J].
Angizi, Shaahin ;
He, Zhezhi ;
Rakin, Adnan Siraj ;
Fan, Deliang .
2018 55TH ACM/ESDA/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2018,
[5]   HOOP: Efficient Hardware-Assisted Out-of-Place Update for Non-Volatile Memory [J].
Cai, Miao ;
Coats, Chance C. ;
Huang, Jian .
2020 ACM/IEEE 47TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2020), 2020, :584-596
[6]  
Chakrabarti DR, 2014, ACM SIGPLAN NOTICES, V49, P433, DOI [10.1145/2660193.2660224, 10.1145/2714064.2660224]
[7]  
Chang KK, 2016, INT S HIGH PERF COMP, P568, DOI 10.1109/HPCA.2016.7446095
[8]  
Coburn J, 2011, ACM SIGPLAN NOTICES, V46, P105, DOI [10.1145/1961295.1950380, 10.1145/1961296.1950380]
[9]  
Condit J, 2009, SOSP'09: PROCEEDINGS OF THE TWENTY-SECOND ACM SIGOPS SYMPOSIUM ON OPERATING SYSTEMS PRINCIPLES, P133
[10]  
Doshi K, 2016, INT S HIGH PERF COMP, P77, DOI 10.1109/HPCA.2016.7446055