Investigation of the Electrical Parameters in a Partially Extended Ge-Source Double-Gate Tunnel Field-Effect Transistor (DG-TFET)

被引:4
作者
Singh, Omendra Kr [1 ]
Dhandapani, Vaithiyanathan [1 ]
Kaur, Baljit [1 ]
机构
[1] Natl Inst Technol Delhi, New Delhi 110040, Delhi, India
关键词
Ambipolarity; band-to-band tunneling (BTBT); linearity; tunnel field-effect transistor (TFET); temperature (T); INTERFACE-TRAP CHARGES; ANALOG PERFORMANCE; FET; IMPACT; LINEARITY;
D O I
10.1007/s11664-024-10997-y
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A partially extended germanium-source double-gate tunnel field-effect transistor (PEGeDG-TFET) utilizes line and point tunneling phenomena to achieve low ambipolar current and high ON-state current. These advantages are accompanied by an exceptionally low OFF-state current (IOFF) and subthreshold swing with resilience against short-channel effects. However, PEGeDG-TFETs face challenges in terms of large variations in IOFF and changes in electrical characteristics with temperature due to the change in the bandgap of semiconductor material. In this article, we explore the temperature-associated variations of a PEGeDG-TFET under the influence of interface trap charges (ITCs) for reliability assessment. Results revealed that the Shockley-Read-Hall phenomenon is dominant at lower gate bias voltage, leading to IOFF degeneration at high temperature. The band-to-band tunneling (BTBT) phenomenon experiences minor variations at higher temperature and gate voltage. Additionally, at high temperature (500 K), it is discovered that the threshold voltage, cut-off frequency, gain-bandwidth product, transconductance-frequency product, intrinsic gain, and transit time decrease, thus limiting the device reliability in the avionics sector where temperatures fall below 410 K with consistent performance of analog/radio-frequency (RF) parameters. This investigation was conducted via simulations on a Silvaco ATLAS simulator considering ITCs and temperature variations.
引用
收藏
页码:2999 / 3012
页数:14
相关论文
共 36 条
[1]   Impact of Gate-Source Overlap on the Device/Circuit Analog Performance of Line TFETs [J].
Acharya, Abhishek ;
Solanki, A. B. ;
Glass, S. ;
Zhao, Q. T. ;
Anand, Bulusu .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (09) :4081-4086
[2]   Linearity and low-noise performance of SOI MOSFETs for RF applications [J].
Adan, AO ;
Yoshimasu, T ;
Shitara, S ;
Tanba, N ;
Fukumi, M .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (05) :881-888
[3]  
[Anonymous], 2016, ATLAS Device Simulation Software
[4]   A High-Performance Inverted-C Tunnel Junction FET With Source-Channel Overlap Pockets [J].
Ashita ;
Loan, Sajad A. ;
Rafat, Mohammad .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (02) :763-768
[5]   Demonstration of a Novel Two Source Region Tunnel FET [J].
Bagga, Navjeet ;
Kumar, Anil ;
Dasgupta, Sudeb .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (12) :5256-5262
[6]   Large Variation in Temperature Dependence of Band-to-Band Tunneling Current in Tunnel Devices [J].
Bizindavyi, J. ;
Verhulst, A. S. ;
Verreck, D. ;
Soree, B. ;
Groeseneken, G. .
IEEE ELECTRON DEVICE LETTERS, 2019, 40 (11) :1864-1867
[7]   Temperature Dependence of Analog Performance, Linearity, and Harmonic Distortion for a Ge-Source Tunnel FET [J].
Datta, Emona ;
Chattopadhyay, Avik ;
Mallik, Abhijit ;
Omura, Yasuhisa .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (03) :810-815
[8]   Study of line-TFET analog performance comparing with other TFET and MOSFET architectures [J].
Der Agopian, Paula Ghedini ;
Martino, Joao Antonio ;
Vandooren, Anne ;
Rooyackers, Rita ;
Simoen, Eddy ;
Thean, Aaron ;
Claeys, Cor .
SOLID-STATE ELECTRONICS, 2017, 128 :43-47
[9]   Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET [J].
Dharmender ;
Nigam, Kaushal .
SILICON, 2021, 13 (07) :2347-2356
[10]   Tunnel field-effect transistors as energy-efficient electronic switches [J].
Ionescu, Adrian M. ;
Riel, Heike .
NATURE, 2011, 479 (7373) :329-337