Superior Threshold-Voltage and On-Resistance Stability in GaN HEMTs Enabled by a Gate ESD Protection Circuit

A gate electrostatic discharge (ESD) protection circuit has recently been deployed in GaN p-gate high electron mobility transistors (HEMTs) to enhance the gate robustness. This on-chip protection circuit clamps the ESD overvoltage to a moderate value and re-directs the transient energy to ground. This work, for the first time, investigates the impact of this ESD protection circuit on the stability of device critical parameters, i.e., threshold voltage (V-th) and on-resistance (R-on). A new industrial device with an on-chip gate ESD protection circuit, as well as a commercial device with a similar gate structure but no protection circuit, are comparatively characterized. Static-stress and pulse-IV tests are used to evaluate the long-term and short-transient parametric shifts, respectively. Devices are stressed under negative gate driving voltage, high drain bias, and high temperature. The device with the ESD protection circuit shows significantly superior stability in Vth and Ron. This is attributable to the suppression of carrier trapping in the gate stack and access region. These results reveal a new pathway to address the inherent parametric instability in p-gate GaN HEMTs, at the same time boosting the gate robustness.