An Asymmetrical 19-Level Inverter with a Reduced Number of Switches and Capacitors

Multilevel inverters are able to provide loads with voltages of high power quality using several DC sources, capacitors, switches, and diodes in their structures. However, the usage of the higher number of semiconductor devices (switches and diodes) and capacitors causes an increase in losses and costs and decreases their efficiency. Thus, lowering the number of switches and capacitors is a challenging issue in designing a multilevel inverter. In this paper, an asymmetrical multilevel inverter is proposed that produces 19-level output voltages. The circuit is composed of nine switches, six diodes, two capacitors, and two isolated DC sources. In comparison with other topologies, the most important advantage of the introduced 19-level topology is the usage of a lower number of switches and capacitors, which leads to a decrease in the number of gate drivers and the total volume of the system. During the charging process, capacitors never connect to each other in series, i.e., they are self-balancing and do not require the extra circuits. The proposed topology offers a total harmonic distortion (THD) of 7.4% in the output voltage, which is less than 8%, complying with the IEEE standards. The performance of the topology is validated under various load conditioning through an experimental setup in the laboratory.