A novel impedance based fault locator algorithm for transmission line

被引:2
|
作者
Kumar, Ravindra [1 ,2 ]
Tripathy, Manoj [1 ]
机构
[1] Indian Inst Technol, Roorkee 247667, India
[2] Power Grid Corp India Ltd, Gurgaon, India
关键词
Fault location estimation error; Fault locator; Superposition current; Transmission line; Fault resistance;
D O I
10.1016/j.epsr.2023.109731
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Accurate fault location reduces the time and cost of an outage. Intelligent Electronic Devices (IEDs) commonly use impedance-based fault location techniques because they are simple and adaptable. This paper presents a novel single-ended impedance-based fault location algorithm. The proposed numerical method calculates the remote end source voltage during the fault in the transmission line. PSCAD/EMTDC-based test system model was developed to simulate the power system faults. The proposed methodology was put into practice using the MATLAB program. The algorithm has been tested on real-time fault data files COMTRADE (Common format for Transient Data Exchnge for Power Systems) taken from IEDs. Several complex tests were performed for singlecircuit/parallel transmission lines to validate the proposed algorithm. The proposed single-ended impedancebased fault location numerical scheme offers higher fault location accuracy, and fault location accuracy is insensitive to fault resistance, load conditions, measurement errors, capacitive current, and decaying DC components.
引用
收藏
页数:13
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