Improved Sense Amplifier Based Flip Flop Design For Low Power And High Data Activity Circuits

An improved power efficient sense amplifier based flip flop is presented which overcomes the issues like glitches at low voltages, speed degradations and power consumptions at higher data activities when compared with previous available sense amplifier Flip Flop (FF) designs. The proposed design uses a detection signal in the sensing stage and a modified single ended latch in the latching stage. An extensive and quantitative comparison between the proposed design and the previously available designs were carried out in 32 nm CMOS technology on T-SPICE. Results showed that the power consumption of the proposed design at nominal voltage is reduced by 14% and at maximum voltage of 1.1 volts by 10%, the overall reduction of 8.3% in Power Delay Product (PDP) is observed at nominal voltage. At frequency of 100 MHz the power consumption is reduced by 15%. In terms of data activities, the power at 100% activity is reduced by 14.2%, at 75% activity by nearly 12%. A 3-bit counter is implemented as an application of the proposed design; power analysis on counter verified the claims that the proposed design is a viable option for low power applications.