Column-Weighted Probabilistic GDBF Decoder for Irregular LDPC Codes

被引：3

作者：

He, Changfu ^{[1
]}

Deng, Keyue ^{[1
]}

Song, Suwen ^{[1
]}

Wang, Zhongfeng ^{[1
]}

机构：

[1] Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Peoples R China

来源：

2023 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, ISVLSI | 2023年

基金：

国家重点研发计划;

关键词：

Low-density parity-check codes; irregular codes; bit-flipping; column-wise weighting factor; hardware implementation;

D O I：

10.1109/ISVLSI59464.2023.10238556

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Existing bit-flipping algorithms, when used for irregular low-density parity-check (LDPC) codes, often suffer from performance degradation due to the imbalance caused by the irregular codeword structure. To alleviate this problem, this paper presents a column-weighted probabilistic gradient-descent bit-flipping (CW-PGDBF) decoder for irregular LDPC codes. Different weighting factors are allocated to variable nodes with different column weights to solve the imbalance. Furthermore, a modified probabilistic flipping rule is employed to reduce the hardware complexity while maintaining the error-correction performance. Simulation results demonstrate that the proposed algorithm can achieve significantly improved performance compared with other BF-based algorithms for irregular codes. Additionally, a hardware architecture for the CW-PGDBF decoder is proposed with acceptable hardware overhead compared to the original PGDBF decoder.

引用

页码：157 / 162

页数：6

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