A current-configurable charge pump with current mismatch compensation for wide output frequency range phase-locked loop

To ensure the loop stability of a wide output frequency range phase-locked loop (PLL), a current-configurable technique for a charge pump (CP) is utilized to reduce the variation of PLL phase margin within a wide frequency range. An isolation transistor is inserted into a traditional current steering CP to improve the clock accuracy and reduce degradation of the PLL lock-in speed caused by switch control signal crosstalk on the output voltage. Furthermore, a feedback-based compensation technique is developed to reduce the mismatch between the charging and discharging currents of the proposed CP, thereby improving PLL output clock accuracy. Based on these techniques, a CP circuit is designed with 0.18 mu m CMOS technology and occupies an active area of 0.005 mm(2). Simulation results from different process corners operated at 1.8 V show that the maximum mismatch between the charging and discharging currents of the CP decrease from 2 % to 0.6 % when the CP current is 10 mu A over a temperature range from -40 degree celsius to 85 degree celsius. The CP is used in a PLL with input and output frequencies of 25-100 MHz and 25-500 MHz, respectively. The worst phase margin of the PLL is improved from 31 degrees to 52.3 degrees by configuring the CP current over a range from 10 to 40 mu A. The output clock accuracy of the PLL is optimized from 600 to 100 Hz/MHz under input and output frequencies of 100 and 500 MHz, respectively.