A Broadband Four-Way Parallel-Series Doherty Power Amplifier for 5G Communications

This article presents a four-way hybrid parallel-series Doherty power amplifier (PA) architecture that supports broadband operation and deep power back-off (PBO) efficiency enhancement for next-generation wireless communication. Most existing load modulation PAs are limited in bandwidth due to the large impedance transformation ratios (ITRs) needed for load-pull matching at deep PBO. The proposed technique achieves wide carrier bandwidth by exploiting different frequency-dependent active load modulations of the parallel/series Doherty combiners and PA path biasing reconfiguration, while the deep PBO efficiency enhancement is realized by the optimum turn-on sequences of the four PA paths. The behavior of the implemented PA load modulation network is mathematically described at different PBO levels corresponding to the output power levels at which each efficiency enhancement occurs. As a proof-of-concept design, a 26-40-GHz PA is implemented in the GlobalFoundries 45-nm CMOS SOI process. The PA measures 22.5-23.9-dBm OP1dB, 26.2%-38.2% PAE(OP1dB), 18.1%-34.5% PAE(6dB) (PBO), and 10.7%- 22.1% PAE(12dB PBO). Note that the PBO levels are referenced from OP1dB. Compared to a normalized ideal class-B PA, this design achieves 1.3-1.8x power-added efficiency (PAE) boost at 6-dB PBO and 1.6-2.3x boost at 12-dB PBO. With a 100-MHz fifth-generation (5G) new radio (NR) frequency range 2 (FR2) 1-CC 64-QAM signal, this PA achieves 9.26-16.9-dBm average output power and 9.9%-25.5% average PAE at an rms error vector magnitude (EVM) of -25 dB for 26-40 GHz. With a 1-CC 400-MHz 16-QAM signal, the PA achieves 12.95-17.4-dBm average output power and 12.5%-27% average PAE at an rms EVM of -20 dB for 26-40 GHz.