共 33 条
[1]
Bhasker J., 2009, Static Timing Analysis for Nanometer Designs: A Practical Approach, Vfirst, P2, DOI [10.1007/978-0-387-93820-2, DOI 10.1007/978-0-387-93820-2]
[2]
Cong J, 2010, FPGA 10, P111
[3]
Donath W. E., 2003, U.S. Patent, Patent No. 6557151
[4]
github, OpenSTA
[5]
Gulati K, 2009, ASIA S PACIF DES AUT, P260, DOI 10.1109/ASPDAC.2009.4796490
[7]
GPU-accelerated Path-based Timing Analysis
[J].
2021 58TH ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC),
2021,
:721-726
[8]
Guo Z., 2020, P IEEE ACM INT C COM, P1
[9]
Differentiable-Timing-Driven Global Placement
[J].
PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022,
2022,
:1315-1320
[10]
Hu J., 2014, P P INT S PHYS DES, P153