List-Serial Pipelined Hardware Architecture for SCL Decoding of Polar Codes

For polar codes, the performance of suc-cessive cancellation list (SCL) decoding is capable of approaching that of maximum likelihood decoding. However, the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously, which are unfriendly to the devices with limited log-ical resources, such as field programmable gate ar-rays (FPGAs). In this paper, we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding, where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the la-tency. Moreover, we employ only one successive can-cellation (SC) decoder core without LxL crossbars, and reduce the number of inputs of the metric sorter from 2L to L + 2. Finally, the FPGA implementa-tions show that the hardware resource consumption is significantly reduced with negligible decoding perfor-mance loss.