A low-power high-throughput link splitting router for NoCs附视频

被引：0
|
作者：
Mohsen SANEEI
Ali AFZALI-KUSHA
Zainalabedin NAVABI
机构：
[1] NanoelectronicsCenterofExcellence,SchoolofElectricalandComputerEngineering,UniversityofTehran,Tehran,Iran
来源：
Journal of Zhejiang University(Science A:An International Applied Physics & Engineering Journal) | 2008年 / 12期
关键词：
Low-power; Latency; Throughput; Network on chip (NoC); Delay-insensitive; Router;
D O I：
暂无
中图分类号：
TN47 [大规模集成电路、超大规模集成电路];
学科分类号：
摘要：
In this paper, we propose a technique for lowering the latency of the communication in a NoC (network on chip). The technique, which can support two qualities of service (QoS), i.e., the guaranteed throughput (GT) and best effort (BE), is based on splitting a wider link into narrower links to increase throughput and decrease latency in the NoC. In addition, to ease the syn-chronization and reduce the crosstalk, we use the 1-of-4 encoding for the smaller buses. The use of the encoding in the proposed NoC architecture considerably lowers the latency for both BE and GT packets. In addition, the bandwidth is increased while the power consumption of the links is reduced.
引用
收藏
页码：1708 / 1714
页数：7
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  • [2] Quality-of-service and error control techniques for mesh-based network-on-chip architectures[J] . Praveen Vellanki,Nilanjan Banerjee,Karam S. Chatha.Integration, the VLSI Journal . 2004 (3)
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    VERHOEFF, T
    [J]. DISTRIBUTED COMPUTING, 1988, 3 (01) : 1 - 8
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