A sample and hold circuit for pipelined ADC

被引：0

作者：

Yutong Zhang ^{[1
,2
]}

Bei Chen ^{[1
,2
]}

Heping Ma ^{[1
,2
]}

机构：

[1] Institute of Semiconductors, Chinese Academy of Sciences

[2] University of Chinese Academy of Sciences

来源：

Journal of Semiconductors | 2018年 / 11期

关键词：

S/H circuit; bootstrapped switch; gain-boosted OTA;

D O I：

暂无

中图分类号：

TN792 [];

学科分类号：

080902 ;

摘要：

A high performance sample-and-hold(S/H) circuit used in a pipelined analog-to-digital converter(ADC) is presented in this paper. Fully-differential capacitor flip-around architecture was used in this S/H circuit.A gain-boosted folded cascode operational transconductance amplifier(OTA) with a DC gain of 90 dB and a GBW of 738 MHz was designed. A low supply voltage bootstrapped switch was used to improve the linearity of the S/H circuit. With these techniques, the designed S/H circuit can reach 94 dB SFDR for a 48.9 MHz input frequency with 100 MS/s sampling rate. Measurement results of a 14-bit 100-MS/s pipeline ADC with designed S/H circuit are presented.

引用

页码：78 / 82

页数：5

共 5 条

[1] A 430 mW 16 b 170 MS/s CMOS pipelined ADC with 77.2 dB SNR and 97.6 dB SFDR[J]. 张辉,李丹,万磊,王海军,高远,朱腓利,王紫琪,丁学欣.Journal of Semiconductors. 2016(03)
[2] An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC
LI Weitao
LI Fule
YANG Changyi
LI Shengjing
WANG Zhihua
[J]. 中国通信, 2015, 12 (05) : 14 - 21
[3] A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC[J] . Yue Sen,Zhao Yiqiang,Pang Ruilong,Sheng Yun.Journal of Semiconductors . 2014 (5)
[4] A 10-bit50-MS/s sample-and-hold circuit with low distortion sampling switches
Zhu Xubin
Ni Weining
Shi Yin
[J]. JOURNAL OF SEMICONDUCTORS, 2009, 30 (05)
[5] A sample - and - hold circuit for 10 - bit 100MS/s pipelined ADC .2 Haitao Wang,Hui Hong,Lingling Sun,et al. IEEE International Conference on ASIC (ASICON) . 2011

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