CMOS implementation of a low-power BPSK demodulator for wireless implantable neural command transmission附视频
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吴朝晖
[1
]
张旭
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State Key Laboratory on Integrated Optoelectronics,Institute of Semiconductors,Chinese Academy of SciencesInstitute of Microelectronics,School of Electronic and Information Engineering,South China University of Technology
张旭
[2
]
梁志明
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Institute of Microelectronics,School of Electronic and Information Engineering,South China University of TechnologyInstitute of Microelectronics,School of Electronic and Information Engineering,South China University of Technology
梁志明
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李斌
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[1] Institute of Microelectronics,School of Electronic and Information Engineering,South China University of Technology
[2] State Key Laboratory on Integrated Optoelectronics,Institute of Semiconductors,Chinese Academy of Sciences
A new BPSK demodulator was presented.By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator,the circuit structure of the demodulator became simpler and hence its power consumption became lower.Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system.The proposed BPSK demodulator was implemented by Global Foundries 0.35μm CMOS technology with a 3.3 V power supply.The designed chip area is only 0.07 mm2 and the power consumption is 0.5 mW.The test results show that it can work correctly.