PARBLO:Page-Allocation-Based DRAM Row Buffer Locality Optimization

被引：1

作者：

米伟 ^{[1
,2
]}

冯晓兵 ^{[1
]}

贾耀仓 ^{[1
]}

陈莉 ^{[1
]}

薛京灵 ^{[3
]}

机构：

[1] Key Laboratory of Computer System and Architecture, Institution of Computing Technology, Chinese Academy of Sciences

[2] Graduate University of Chinese Academy of Sciences

[3] Programming Languages and Compilers Group, School of Computer Science and Engineering University of New South Wales

来源：

Journal of Computer Science & Technology | 2009年 / 24卷 / 06期

关键词：

DRAM; row buffer; page allocation; locality optimization;

D O I：

暂无

中图分类号：

TP333 [存贮器];

学科分类号：

081201 ;

摘要：

DRAM row buffer conflicts can increase memory access latency significantly. This paper presents a new page-allocation-based optimization that works seamlessly together with some existing hardware and software optimizations to eliminate significantly more row buffer conflicts. Validation in simulation using a set of selected scientific and engineering benchmarks against a few representative memory controller optimizations shows that our method can reduce row buffer miss rates by up to 76% (with an average of 37.4%). This reduction in row buffer miss rates will be translated into performance speedups by up to 15% (with an average of 5%).

引用

页码：1086 / 1097

页数：12