A 12-bit 40-MS/s SHA-less pipelined ADC using a front-end RC matching technique

被引：3

作者：

范明俊 ^{[1
]}

任俊彦 ^{[1
,2
]}

舒光华 ^{[1
]}

过瑶 ^{[3
]}

李宁 ^{[1
]}

叶凡 ^{[1
]}

许俊 ^{[1
]}

机构：

[1] State Key Laboratory of ASIC & Systems Fudan University

[2] Micro-Nanoelectronics Science and Technology Innovation Platform,Fudan University

[3] The MediaTek Inc

来源：

半导体学报 | 2011年 / 32卷 / 01期

关键词：

analog-to-digital converter; opamp-sharing; RC matching; SHA-less; low-power;

D O I：

暂无

中图分类号：

TN792 [];

学科分类号：

080902 ;

摘要：

<正>A 12-Bit 40-MS/s pipelined analog-to-digital converter(ADC) incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation.Employing SHA-less,opampsharing and low-power opamps for low dissipation and low cost,designed in 0.13-μm CMOS technology,the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range,60.5-dB of signal-to-noise-and -distortion ratio,and -75.5-dB of total harmonic distortion(the first 5 harmonics included) while consuming 15.6-mW from a 1.2-V supply.

引用

页码：85 / 89

页数：5

共 11 条

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