Fast Fourier transform processor architecture

This paper describes a VLSI architecture used for implementation offast Fourier transform,of which the computation cell(CC)implement the com-putation of 4-point DFT and multiplication of twiddle factors using radix-4pipeline computation method,and the address generator(AG)gives the ad-dresses of both transform data and twiddle factors simultaneously.In addition,this paper also presents the recursive and cascade circuit configurations usingthe CC,AG and BFP overflow preventing scheme.Up to 64K-point FFT canbe computed quickly and flexibly by using these two circuit configurations.