A novel high performance ESD power clamp circuit with a small area附视频

被引:0
作者
杨兆年
刘红侠
李立
卓青青
机构
[1] KeyLaboratoryoftheMinistryofEducationforWideBand-GapSemiconductorMaterialsandDevices,SchoolofMicroelectronics,XidianUniversity,Xi'an,China
关键词
electrostatic discharge; clamp circuit; false triggering; turn-off mechanism;
D O I
暂无
中图分类号
TN386 [场效应器件];
学科分类号
摘要
<正>A MOSFET-based electrostatic discharge(ESD) power clamp circuit with only a 10 ns RC time constant for a 0.18-μm process is proposed.A diode-connected NMOSFET is used to maintain a long delay time and save area.The special structure overcomes other shortcomings in this clamp circuit.Under fast power-up events,the gate voltage of the clamp MOSFET does not rise as quickly as under ESD events,the special structure can keep the clamp MOSFET thoroughly off.Under a falsely triggered event,the special structure can turn off the clamp MOSFET in a short time.The clamp circuit can also reject the power supply noise effectively.Simulation results show that the clamp circuit avoids fast false triggering events such as a 30 ns/1.8 V power-up,maintains a 1.2 /μs delay time and a 2.14μs turn-off time,and reduces to about 70%of the RC time constant.It is believed that the proposed clamp circuit can be widely used in high-speed integrated circuits.
引用
收藏
页码:124 / 130
页数:7
相关论文
共 2 条
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MICROELECTRONICS RELIABILITY, 2003, 43 (07) :987-991
[2]  
Whole-chip ESD protection design with efficient VDD-to-VSS clamp circuit for submicron CMOS VLSI .2 M.-D. Ker. IEEE Trans. Electron Devices . 1999