共 10 条
[1]
A mixed-signal built-in self-test approach for analog cir- cuits. Charles Stroud,Jason Morton,Atia Islam et al. Proceedings of IEEE Southwest Sympo- sium on Mixed-Signal Design . 2003
[2]
BIST for D/A and A/D converters. Arabi K,Kaminska I,Janusz Rzeszut. IEEE Design and Test of Com- puters . 1996
[3]
A BIST scheme for on-chip ADC and DAC test- ing. Huang Jiun-Lang,Ong Chee-Kian,Cheng Kwang-Ting. Proceedings of Europe Conference and Ex- hibition on Design, Automation and Test . 2000
[4]
Optimal schemes for ADC BIST based on histogram. Wang Yongsheng,Wang Jinxiang,Lai Fengchang et al. IEEE 14th Asian Proceedings on Test Symposium . 2005
[5]
A complete BIST scheme for ADC linearity testing. Wu Guanglin,Ling Ming,Rao Jin et al. IEEE Proceedings on Solid-State and Integrated Circuits Technology . 2004
[6]
A low-cost BIST scheme for ADC testing. Wang Yongsheng,Wang Jinxiang,Lai Fengchang et al. Proceedings of IEEE 6th International Conference on ASIC . 2005
[7]
Built-in high resolution signal generator for testing ADC and DAC. Chang Yeong-Jar,Chang Soon-Jyh,Ho Jung-Chi et al. Proceedings of IEEE Interna- tional Symposium on VLSI Technology, Systems, and Appli- cations . 2003
[8]
An ADC-BiST scheme using sequential code analysis. Erdogan E S,Ozev S. Proceedings of Europe Conference and Exhibition on Design, Automation and Test . 2007
[9]
A low-cost adaptive ramp generatorfor analog BIST applications. Azais F,Bernard S,Bertrand Y et al. 19th IEEE Proceedings on VLSI Test Sympo- sium . 2001
[10]
Analog BIST generator for ADC testing. Bernard S,Azais F,Bertrand Y et al. Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems . 2001