Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

A radiation hard phase-locked loop (PLL) is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time < 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter < 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.