A 14-bit 500-MS/s DAC with digital background calibration

被引：0

作者：

徐震 ^{[1
]}

李学清 ^{[2
]}

刘嘉男 ^{[2
]}

魏琦 ^{[2
]}

骆丽 ^{[1
]}

杨华中 ^{[2
]}

机构：

[1] School of Electronic and Information Engineering, Beijing Jiaotong University

[2] Circuits and System Laboratory, Department of Electronic Engineering, Tsinghua University

来源：

Journal of Semiconductors | 2014年 / 03期

关键词：

digital to analog converter(DAC); current-steering; digital background calibration;

D O I：

暂无

中图分类号：

TN792 [];

学科分类号：

080902 ;

摘要：

Thelinearityofcurrent-steeringdigital-to-analogconverters(DACs)atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matching. This, however, results in large gradient errors and parasitic capacitance, which degrade the spurious free dynamic range(SFDR) for high-frequency signals. To overcome this problem, calibration is an effective method.In this paper, a digital background calibration technique for current-steering DACs is presented and verified by a 14-bit DAC in a 0.13 m standard CMOS process. The measured differential nonlinearity(DNL) and integral nonlinearity(INL) are 0.4 LSB and 1.2 LSB, respectively. At 500-MS/s, the SFDR is 70 dB and 50.3 dB for signals of 5.4 MHz and 224 MHz, respectively. The core area is 0.69 mm2and the power consumption is 165 mW from a mixed power supply with 1.2 V and 3.3 V.

引用

收藏

页码：156 / 161

页数：6

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