A self-biased PLL with low power and compact area

被引:0
作者
贾海珑
陈先敏
刘琦
冯光涛
机构
[1] DesignServiceCenter,SemiconductorManufacturingInternational(Shanghai)Corp
关键词
self-biased PLL; ring VCO; low power; compact area;
D O I
暂无
中图分类号
TN911.8 [相位锁定、锁相技术];
学科分类号
081002 ;
摘要
A new low power,low phase jitter,compact realization,and self-biased PLL,which is fabricated on SMIC 40 nm CMOS technology is introduced.The proposed self-biased PLL eliminates extra band gap biasing circuits,and internally generates all the biasing voltages and currents.Meanwhile,all of the PLL dynamic loop parameters,such as loop bandwidth,natural frequency,damping factors are kept constant adaptively.By optimizing the circuit structures,the perfect unity of chip estate,power dissipation,phase jitter,and loop stability is achieved.The PLL consumes 4.2 m W of power under 1.1 V/2.5 V voltage supply at 2.4 GHz VCO frequency,while occupying a die area of less than 0.02 mm2(180110 m2/,and the typical period jitter(RMS) is around 2.8 ps.
引用
收藏
页码:132 / 136
页数:5
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