On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs

被引：0
作者：
Jiaqi Yang [1 ]
Ting Li [2 ]
Mingyuan Yu [1 ]
Shuangshuang Zhang [1 ]
Fujiang Lin [1 ]
Lin He [1 ]
机构：
[1] Institute of MESIC,University of Science and Technology of China
[2] Science and Technology on Analog Integrated Circuit Laboratory
来源：
Journal of Semiconductors | 2017年 / 08期
基金：
中国国家自然科学基金; 中央高校基本科研业务费专项资金资助;
关键词：
analog-to-digital conversion; successive approximation; low-power; high-speed; internal switching activities;
D O I：
暂无
中图分类号：
TN792 [];
学科分类号：
080902 ;
摘要：
This paper analyzes the power consumption and delay mechanisms of the successive-approximation(SA) logic of a typical asynchronous SAR ADC,and provides strategies to reduce both of them.Following these strategies,a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate.The unnecessary internal switching power of a typical TSPC DFF,which is commonly used in the SA logic,is avoided.The delay of the ready detector as well as the sequencer is removed from the critical path.A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS.It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate,and has a total power consumption of 555 μW,while the digital part consumes only 203 μW.
引用
收藏
页码：91 / 96
页数：6
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