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CIRCUIT TESTABLE DESIGN AND UNIVERSAL TEST SETS FOR MULTIPLE-VALUED LOGIC FUNCTIONS
被引:0
作者:
Pan Zhongliang (School of Physics and Telecommunication Engineering
机构:
基金:
中国国家自然科学基金;
关键词:
Multiple-valued logic;
Testable realization;
Single faults;
Bridging faults;
Skew faults;
D O I:
暂无
中图分类号:
TM13 [电路理论];
学科分类号:
080804 ;
080805 ;
摘要:
The circuit testable realizations of multiple-valued functions are studied in this letter. First of all,it is shown that one vector detects all skew faults in multiplication modulo circuits or in addi-tion modulo circuits,and n+1 vectors detect all skew faults in the circuit realization of multiple-valued functions with n inputs. Secondly,min(max) bridging fault test sets with n+2 vectors are pre-sented for the circuit realizations of multiple-valued logic functions. Finally,a tree structure is used instead of cascade structure to reduce the delay in the circuit realization,it is shown that three vec-tors are sufficient to detect all single stuck-at faults in the tree structure realization of multiple-valued logic functions.
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页码:138 / 144
页数:7
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