A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp

被引：0
|
作者：
潘红伟 [1 ]
刘斯扬 [1 ]
孙伟锋 [1 ]
机构：
[1] National ASIC System Engineering Research Center,Southeast University
来源：
Journal of Semiconductors | 2013年 / 01期
关键词：
ESD protection; ESD robustness; SCR-LDMOS; latch-up; holding voltage;
D O I：
暂无
中图分类号：
TN386.1 [金属-氧化物-半导体（MOS）器件];
学科分类号：
0805 ; 080501 ; 080502 ; 080903 ;
摘要：
The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD(electro-static discharge) clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.
引用
收藏
页码：53 / 57
页数：5
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