TRSTR: A Fault-Tolerant Microprocessor Architecture Based on SMT

被引:0
作者
YANG Hua CUI Gang YANG XiaozongFaulttolerant Computing Lab Harbin Institute of Technology Harbin Heilongjiang China [150001 ]
机构
关键词
fault-tolerant; high-performance; simultaneous multithreading; architecture;
D O I
暂无
中图分类号
TP332 [运算器和控制器(CPU)];
学科分类号
081201 ;
摘要
Based on Simultaneous Multithreading (SMT), we propose a fault-tolerant scheme called Tri-modular Redundantly and Simultaneously Threaded processor with Recovery (TRSTR). TRSTR features as following: First, we introduce an arbitrator context into the conventional SRT (Simultaneous and Redundantly Threaded), which acts as an arbitrator when results from the other two contexts disagree, or acts as an ordinary thread generally, thus making full use of SMT’s parallelism. Second, we append reconfigurable feature to sphere of replication in SRT, making it more flexible for changing demands and situations. Third, TRSTR has two working modes: Tri-Simultaneous with Voting (TSV) and Dual-Simultaneous with Arbitrator (DSA), which can switch at will. Finally, in addition to transient-fault coverage, TRSTR has on-line self-checking and self-recovering abilities, so as to shield off some permanent faults and reconfigure itself without stopping the crucial job, improving its reliability and availability.
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页码:51 / 55
页数:5
相关论文
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[2]  
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