Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit

被引：0

作者：

刘晓贤 ^{[1
]}

朱樟明 ^{[1
]}

杨银堂 ^{[1
]}

王凤娟 ^{[1
]}

丁瑞雪 ^{[1
]}

机构：

[1] Microelectronics School, Xidian University

来源：

Chinese Physics B | 2014年 / 23卷 / 03期

基金：

中国国家自然科学基金;

关键词：

three-dimensional integrated circuit; through silicon via channel; signal reflection; S-parameters;

D O I：

暂无

中图分类号：

TN405.97 [互连及多层布线技术];

学科分类号：

080903 ; 1401 ;

摘要：

The through silicon via(TSV) technology has proven to be the critical enabler to realize a three-dimensional(3D)gigscale system with higher performance but shorter interconnect length. However, the received digital signal after transmission through a TSV channel, composed of redistribution layers(RDLs), TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflection of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient(S11) and signal transmission coefficient(S21) are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance(RLGC)elements of the TSV channel are iterated from scattering(S)-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure(HFSS) simulation software by Ansoft.

引用

页码：587 / 594

页数：8